In a CMOS circuit (a complementary circuit), the power consumption is proportional to the square of the power supply voltage. Therefore, it is effective to reduce the power supply voltage for reducing the power consumption of a CMOS LSI. However, as the power supply voltage is reduced, the driving power of the transistor decreases, thereby posing a problem of an increase in the delay time of the circuit. This problem becomes more significant the more the power supply voltage is reduced. Particularly, it has been known that the increase becomes significant when the power supply voltage is three times the threshold or less.
A possible way to improve this is to reduce the threshold. However, as the threshold is reduced, the leak current when the gate is OFF increases, the lower limit of the threshold is defined by the acceptable OFF current.
In order to alleviate such a problem, there has been proposed, as a transistor for a low power supply voltage, a dynamic threshold operation transistor which realizes a high driving power at a low voltage by reducing an effective threshold when a transistor is ON (A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation, F. Assaderaghi et al., IEDM94 Ext. Abst. p.809).
FIG. 19 illustrates a simplified structure of such a dynamic threshold operation transistor (hereinafter, referred to as a "DTMOS"). While a NMOS is illustrated, a PMOS can also be realized with symmetrically opposite polarities.
As illustrated in the figure, an SOI substrate 1 is used, and a gate 3 and the substrate 1 are locally short-circuited with an oversized metal line 2. The essential element is the short-circuiting of the gate 3 and the substrate 1 with each other, and the way they are short-circuited is not limited to the one illustrated.
When a gate bias is applied in the structure in which the gate and the substrate are short-circuited, a forward bias of the same magnitude as the gate bias is applied to a substrate active region. Thus, the same biased state as that in an ordinary translstor results when the gate is OFF. When the gate is ON, the substrate is forwardly biased as the gate bias increases. As a result, the threshold decreases.
However, in this structure, it is necessary, for suppressing the stand-by current, to limit the voltage applied to the gate to about 0.6 V, a voltage at which a lateral parasitic bipolar transistor ts turned ON.
When the gate bias (=body bias) is OPP, such a DTMOS has a leak current comparable to that of an ordinary transistor provided on an SOI substrate and having the same channel state. While the DTMOS is ON, as the gate bias (=body bias) increases, the threshold further decreases, whereby the gate overdrive effect increases, thereby significantly increasing the driving power. The fact that deterioration of mobility is suppressed by the suppression of a vertical electric field on the substrate surface also contributes to the increase in the driving power. Moreover, since the lateral parasitic bipolar transistor is OFF, the significant increase in the stand-by current is suppressed.
However, since the above-described conventional DTMOS uses an SOI substrate, the thickness of the body (the depth of the channel region) is very small (50 nm-200 nm), thereby resulting in a very high resistance. Thus, even if the gate and the body are short-circuited with each other via a contact, a potential is less likely to be transferred to the body at a position farther away from the contact, and the CR time constant increases. Therefore, in view of a transient operation, the effect as a DTMOS is suppressed, and it cannot be operated at a high speed.
Thus, the present invention has been made to solve such problems in the prior art, and has an objective of providing a semiconductor device which realizes a dynamic threshold operation assuming the application of a bulk semiconductor substrate in order to solve the increase in the body resistance of the SOI substrate.